Changing PLL settings without a new compilation

[Altera_Forum]

Hi,  

I am using Arria V GX FPGA and Quartus 13.1 and there are timing violations, so I need to try different PLL settings to try to fix them. Is there a way to change the PLL phase shift for example, without changing it in Megawizard and running a complete compilation? I tried in the Resource Property Editor but all the fields are greyed out and can't be edited. Or is it possible to run only a new timing analysis for another phase shift?  Thanks.

[Altera_Forum]

There is a way, but it's not very simple. 

 If you generate the PLL with ALTPLL_RECONFIG, instead of ALTPLL you can reprogram the PLL from within the operating system. This is usually done with a CPU either inside or outside of the block, but a few canned configurations could be setup into block rams, and initiated with a state machine if you needed to test a few configurations.  I suggest you read up on this: http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf  Regards,  Pete

[Altera_Forum]

Using dynamically configurable PLLs is a very powerful way to explore various configurations. So, it is well worth investing the time to get to grips with it. It becomes a very useful tool to fine tune interfaces, especially with external peripherals. If you can stomach instantiating a Nios to control it you will realise an enormous amount of flexibility. 

 However, I'm not sure I'd expect it to solve all your timing violations - assuming they're internal violations you're referring to. Shifting the phase of a clock is not going to benefit any block of logic that resided entirely on that clock domain. Are we discussing cross domain issues? Perhaps you can shed a little more light on the timing violations you have.  Regards, Alex

[Altera_Forum]

--- Quote Start ---  Using dynamically configurable PLLs is a very powerful way to explore various configurations. So, it is well worth investing the time to get to grips with it. It becomes a very useful tool to fine tune interfaces, especially with external peripherals. If you can stomach instantiating a Nios to control it you will realise an enormous amount of flexibility.   --- Quote End ---    Alex,  How do you analyse the results with timing analyser, or do you just accept the analysis will fail but that you can fix it by varying some PLL properties?  How do you know that things are 'working' properly?  I've never used dynamic configuration of anything that would affect the timing analysis but am interested in what's involved.  Nial

[Altera_Forum]

Hi Nial: 

 The problem, is you are dynamically changing the timing, so the static timing analyzer of Quartus will have way to determine timing for you.  I have only used this for interface adjustments, (IE external high speed interfaces). And had a system with two clocks, a "Launch" clock and a "Latch Clock" across the interface that were skewed compared to each other.  To determine the best setting, we found the failing boundary on both sides, and then picked a selection in the middle of the passing window.  Internal timing should be left to the tool to work out and correct. If you are still failing timing, you should look at re-pipelining the design, or optimizing the layout.  Pete