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I have simulated a 2048 point FFT v2.2.1 (streaming) in both ModelSim and Quartus. In Quartus correct streaming behaviour is observed, with assertion of master_source_sop immediately following assertion master_source_eop, and master_source_ena remaining high at all times.
When simulating the VHO file in ModelSim incorrect behaviour is observed, with a gap between master_source_eop and master_source_sop assertions, during which time master_source_ena is taken low. Attached are the plots of what I have described. Does anyone know of a solution to this problem? (Besides trying the latest ver FFT core which is not an option)Link Copied
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Hello Wilhelm,
if the error is with the FFT compiler generated simulation model, who about Modelsim gate level simulation of the Quartus compiled FFT design? I guess, the simulation model may be faulty. Regards, Frank- Mark as New
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Hello Wilhelm,
I had the occasion to test FFT v2.2.0 with a similar configuration (streaming 2048, 8 bit), but my Modelsim output was continuous with master_souce_sop following master_source_eop immediately. I don't know, if the input to your FFT was also continuous. I used the Altera supplied testbench and test data.with Modelsim DE 6.2f. Regards, Frank- Mark as New
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Thanks for the response Frank. I did try regenerating the VHO using the post synthesis netlist generation as you suggested. This has fixed my problem but of course results in considerably slower simulations.
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Hello Wilhelm.
gate level simulation should be used, if the synthesis result is in doubt or device timing is the object of tests. But the Altera supplied functional simulation model should produce corect results as well. As reported, I experienced no irregularities with FFT v.2.2.0 model. Don't know if the difference is related to V2.2.1 model, the testbench or ModelSim version. Anyway, the real design behaviour counts. Best regards, Frank
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