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The following code snippet does not synthesize with the native Quartus synthesis tool, which supposedly supports System Verilog (The SV compile switch is set in Quartus):
typedef struct packed{ bit[9:0] A; bit B; bit C; bit D; bit E; bit F; bit[9:0] G; bit[1:0] H; bit I; }packed_struct; <line 140> packed_struct [10:0] array_of_structs; I get the following error: Error (10168): SystemVerilog Declaration error at *.v(140): prefix for packed array type does not refer to a packable type :confused: System Verilog does support packed arrays of packed structures. What is the problem? ModelSim SE compiles and simulates the structure above. Quartus synthesis chokes.Link Copied
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--- Quote Start --- The following code snippet does not synthesize with the native Quartus synthesis tool, which supposedly supports System Verilog (The SV compile switch is set in Quartus): typedef struct packed{ bit[9:0] A; bit B; bit C; bit D; bit E; bit F; bit[9:0] G; bit[1:0] H; bit I; }packed_struct; <line 140> packed_struct [10:0] array_of_structs; I get the following error: Error (10168): SystemVerilog Declaration error at *.v(140): prefix for packed array type does not refer to a packable type :confused: System Verilog does support packed arrays of packed structures. What is the problem? ModelSim SE compiles and simulates the structure above. Quartus synthesis chokes. --- Quote End --- Hi, I'm not an expert for System Verilog, but running successful a simulation does not mean that the code could be also synthesize. The version 8.0 is an old one, maybe your required feature is implemented in the newest version 9.0 SP2. Kind regards GPK
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Thanks, but it doesnt work in 9.0 sp2 either. Same error.
I understand that all things simulatable are not synthesizable, but this is one of those SV constructs that really should be supported by synthesis tools--and in fact is supported by Synplify Pro, et al. I'll have to use Syn Pro I suppose...- Mark as New
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--- Quote Start --- Thanks, but it doesnt work in 9.0 sp2 either. Same error. I understand that all things simulatable are not synthesizable, but this is one of those SV constructs that really should be supported by synthesis tools--and in fact is supported by Synplify Pro, et al. I'll have to use Syn Pro I suppose... --- Quote End --- Hi, you should send a service request to Altera, in order to get the feature build-in. Kind regards GPK
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I had the same issue, and suspect it is simply an unsupported SystemVerilog feature in Quartus II. I was able to make an unpacked structure work. Make the following change to line 140:
<line 140> packed_struct array_of_structs [10:0]; I hope this works for you. -mark- Mark as New
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I face the same issue in Quartus 9.1. The suggested solution is not always acceptable: One problem with unpacked arrays is that you can't use them to interface between two modules. Is there any intention to support a packed arrays of packed struct in future Quartus releases? Has someone raised an SR?
Thanks.
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