Timequest Constraints for Asynchronous RAM and SPI-like Input Devices

[Altera_Forum]

I'm new to Timequest. In my designs I use a couple of types of interface that I'm not sure how to write suitable Timequest constraints for and would like some help and examples if possible. 

  The first and probably most straightforward is SPI-like devices where the FPGA provides the clock and the device sends data to the FPGA (e.g., a serial ADC.) The clock provided by the FPGA is a divided-down version of the main FPGA clock and is only active when a data transfer is taking place. What are the appropriate constraints for this situation?   Going through the Timequest tutorial I've seen examples for Synchronous I/O where all the devices are clocked by a common board clock, but they do not explain how to write constraint when the FPGA derives a clock to drive peripherals. The examples for source-synchronous interfaces do not appear to be applicable either, as in those cases the device or FPGA provide both the clock and data, whereas in my case the FPGA provides the clock and the peripheral provides the data.   The second interface I'm having trouble understanding how to write Timequest constraints for is an asynchronous RAM. I have a RAM controller block that provides a synchronous interface to the rest of the logic in the FPGA and implements a state machine to control the address, data and control lines to the RAM to perform reads and writes. The controller latches the address and output data in registers and asserts the output enable or write enable to perform the read or write respectively. The write enable signal is passed through a register clocked on the falling edge of the clock to give time for the address lines to stabilize. Input data is registered on the second clock cycle after the output enable line is asserted.   I have seen an example of an SDC file for asynchronous RAM interface posted on this forum, but have had little success in adapting it to the RAM interface described above.   A search of this forum has not brought up any answers and Rysc's Timequest tutorial, while very useful does not appear to address these two situations.   Any help on either or both would be much appreciated!   Robert

[Altera_Forum]

This thread has an example on constraining Quad SPI flash devices, and includes a discussion about generated clocks and multi-cycle constraints: 

 http://www.alteraforum.com/forum/showthread.php?t=41009  Cheers, Dave

[Altera_Forum]

Thanks Dave. I'll have a look at the attached PDF later as the Websense filter at work is blocking access to the URL under the guise of it being a source of "streaming-media". 

 Robert

[Altera_Forum]

Hi Robert, 

  --- Quote Start ---   I'll have a look at the attached PDF later as the Websense filter at work is blocking access to the URL under the guise of it being a source of "streaming-media".   --- Quote End ---   You should be able to use the direct link on this page:  http://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html  Cheers, Dave

[Altera_Forum]

Thanks Dave, your Timequest constraints for SPI appear to be precisely what I was after and will probably help me with the asynchronous RAM interface as well. 

 Robert

[Altera_Forum]

Hi Robert, 

  --- Quote Start ---  Thanks Dave, your Timequest constraints for SPI appear to be precisely what I was after and will probably help me with the asynchronous RAM interface as well.   --- Quote End ---    I had some questions about SRAM at one point too ... there's another PDF + zip file with this thread  http://www.alteraforum.com/forum/showthread.php?t=31457  Cheers, Dave

[Altera_Forum]

That looks useful as well. It would be great if Altera could put examples of this stuff in the Timequest documentation. 

 Robert