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I am working on a simple cache simulator for recent Intel processors. It's used to provide profiling info for our cache optimization. Therefore, I don't need it to be very very accurate, but it can't be too different from the facts either.
I didn't find much information about cache line replacement policy. Does anyone know where I can look up these info? I am mostly interested in L2 and L3 cache replacement policies. Someone online said it's PLRU. Can anyone confirm that? If yes, is it a tree-PLRU or bit-PLRU?
Thanks.
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Yes, it is PLRU: Three-LRU bit in specific.
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Wait, I just found a problem. How do you use 3 LRU bits to handle 16-way set associative L3 slices? I previously thought you were referring to using 3 bits in a 4-way set associative similar to SCC L2. (/servlet/JiveServlet/previewBody/5753-102-1-8879/L2cache.pdf http://communities.intel.com/servlet/JiveServlet/previewBody/5753-102-1-8879/L2cache.pdf)
Is it just a similar implementation where you use 5 bits to walk the tree?
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You may want to post this query to the Intel(R) Software Network forums: http://software.intel.com/en-us/forum Forums | Intel® Developer Zone
I am escalating this internally to see if this information is available through this support channel; still, please contact the Software Network forums.
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