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Hello guys
I have one more problem with the altera Vhdl code using max_plus_II I wirte this simple code : ibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity PWM_n4 is port ( clk48Mhz : in std_logic; encoder : in std_logic_vector(13 downto 1); cntr_in : in std_logic_vector(12 downto 0); out_signal : out std_logic ); end; architecture arc_PWM_n4 of PWM_n4 is signal signal_out : std_logic := '0'; signal cntr : integer range 0 to 4861 := 0; signal reset_cntr : std_logic := '0'; signal n_encoder : std_logic_vector(13 downto 1) := encoder; signal reset_encoder : std_logic := '1'; begin process begin if rising_edge(clk48Mhz) then if reset_cntr = '1' then cntr <= 0; else cntr <= cntr + 1; end if; if reset_encoder = '1' then n_encoder <= encoder; end if; end if; end process; process(clk48Mhz) begin if falling_edge(clk48Mhz) then reset_cntr <= '0'; reset_encoder <= '0'; if cntr = cntr_in then if signal_out = '1' then signal_out <= '0'; else signal_out <= '1'; end if; else if cntr = 4860 then signal_out <= '1'; else if cntr = 4861 then reset_cntr <= '1'; reset_encoder <= '1'; end if; end if; end if; end if; end process; out_signal <= signal_out; end; when I simulate this code I got the results I need, but when I connect this code to a output pin and the pin to a scope, the scope shows me the opposite of what the simulator shows. what should I do, why it is behave like that? it should be the same not the opposite. thx a lotLink Copied
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scope not scoop :(
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Hi
Which one is correct?? I mean the simulated stuff or the actual signal on the pin. check up your simalution and synthesis settings.... my guess is in either of this you are enabling inverted output generation..- Mark as New
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try adding a reset signal
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I would try adding asynchronous reset signal. It would look something like this:
begin process begin if asynchronous_reset = '1' then --here you can put init values to signals, for example: out_signal <= (others => '0'); elsif rising_edge(clk48Mhz) then if reset_cntr = '1' then cntr <= 0; else cntr <= cntr + 1; end if; if reset_encoder = '1' then n_encoder <= encoder; end if; end if; end process; I assume that your output is logically inverted. You can also add simple output inverter. It will solve your problem easily :)
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