- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi;
I try write a code for convert integer to ufixed: package my_data_types is type vector is array (natural range <>) of integer; type ufixed is array (natural range <>) of std_logic; end my_data_types; library ieee; library ieee_proposed; use ieee_proposed.fixed_pkg.all; use work.my_data_types.all; entity fix is port (clk: in bit; nprev: in vector (0 to 7); ip1: out ufixed (3 downto -4)); end fix; architecture fix of fix is signal n1: ufixed (3 downto -4); begin process(clk) begin if (clk'event and clk='1') then for i in 0 to 7 loop ip1(i) <= to_ufixed (nprev(i),n1); end loop; end if; end process; end fix; I get this error: Error (10482): VHDL error at fix.vhd(3): object "std_logic" is used but not declared. How to declare the "std_logic" in package?..Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
First of all. DO NOT declare your own version of ufixed, it is in the fixed_pkg library. You are going to have problems if you do this.
Secondly, you need to include the line: library ieee; use ieee.std_logic_1164.all;- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
What the right way to declare ufixed as an array?..thanks for reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
you dont need this
type ufixed is array (natural range <>) of std_logic; It is already declared in the fixed_pkg.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Now I get this error:
Error (10511): VHDL Qualified Expression error at fix.vhd(23): to_ufixed type specified in Qualified Expression must match std_ulogic type that is implied for expression by context. At this line: ip1(i) <= to_ufixed (nprev(i),n1); Why?..thanks for reply- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
ip1(i) is a single bit. You cannot assign an entire array (the ufixed) to a single bit.
You need to decalre an array of ufixed values.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sorry Tricky, I don't get what you say. How to declare an array of ufixed values? Thanks for reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
type ufixed_array_t is array(natural range <>) of ufixed(3 downto -4);
signal a : ufixed_array_t(0 to 7); etc- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
This is my package code:
package my_data_types is type vector is array (natural range <>) of integer; type ufixed_array_t is array (natural range <>) of ufixed (3 downto -4); end my_data_types; But then, error said: Error (10482): VHDL error at fix.vhd(3): object "ufixed" is used but not declared How to avoid this error?..Thanks for reply- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
you need to include the fixed_pkg.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I already include the fixed_pkg..
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
you clearly didnt for the package. you have to have separate library imports for each package and entity
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
What do you mean by "separate library imports for each package and entity"?
Thanks for reply- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
in your code, you have the package above the library includes.
you need to do this:
--libraries for the package
library ieee;
use ieee.std_logic_1164.all;
library IEEE_Porposed;
use IEEE_Proposed.fixed_pkg.all;
package my_package is
....
end package;
--Now the libraries for the entity
library ieee;
use ieee.std_logic_1164.all;
library IEEE_Porposed;
use IEEE_Proposed.fixed_pkg.all;
use work.my_package.all;
Usually, you would put the package and entity in a separate file.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks Tricky..I learn a lot from you. I appreciate it.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
May I suggest you read a VHDL tutorial - a lot of the questions you are asking are very very basic.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yes, I will. Since now, I still learn form vhdl tutorial and other materials for my better understand.Thanks for the advise =)
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page