zero-delay buffer PLL issue

[Altera_Forum]

Hi, 

I've recently started using Altera's PLLs for a Cyclone V project. I'm creating a PLL, with the IP Wizard, with zero-delay buffer (zdbfbclk) mode enabled. I want to use the zdbfbclk port to drive the clock signal I desire. However, I have not connected the single out clock port to anything. This results in the following warning: Warning: OUTCLK port on the PLL is not properly connected on instance pllTdm:pllTdmI|pllTdm_0002:plltdm_inst|altera_pll:altera_pll_i|general[0].gpll. The output clock port on the PLL must be connected.  What is the proper way of connecting this port? Do I really need it? Am I correct in assuming the zdbfbclk can provide the clock signal I desire? Any pointers/references to using this mode properly would be great.  Thanks in advance.

[Altera_Forum]

Have a look at the altera iopll ip core user guide (http://www.altera.com/literature/ug/ug_altera_iopll.pdf). To quote from it: 

   --- Quote Start ---  If you select the zero delay buffer mode, the PLL must feed an external clock output pin  --- Quote End ---   So yes, you must connect it up.  Regards, Alex